Data read-write circuit and method therefor, memory and driving method therefor, and electronic device

A data read/write circuit, comprising:

• a memory cell, configured to store data and comprising a storage transistor and a write transistor that are connected with each other;
• a data signal line, connected to the storage transistor and configured to:
• supply a first reference voltage to the storage transistor in a standby stage and a pre-charging stage, write data into the storage transistor in a data writing stage, and read data in response to whether the storage transistor is turned on in a data reading stage;
• and
• an auxiliary signal line, connected to the storage transistor and the write transistor, and configured to:
• supply the first reference voltage to both the storage transistor and the write transistor in the standby stage and the pre-charging stage, be floated in the data writing stage, and supply a second reference voltage to both the storage transistor and the write transistor in the data reading stage,
• wherein a sum of a maximum data voltage corresponding to the data and a threshold voltage of the storage transistor is a reference voltage;
• and the first reference voltage is greater than the reference voltage.

A memory comprising:

• at least one memory cell, and a first bit line, a second bit line, a first word line, and a second word line that are correspondingly connected to the memory cell;
• wherein the memory cell comprises:
• a storage transistor and a write transistor;
• the storage transistor comprises a storage gate, a first gate, a first electrode, and a second electrode;
• and the write transistor comprises a second gate, a first electrode, and a second electrode;
• the storage gate is connected to the first electrode of the write transistor, and an intersection point where the storage gate is connected to the first electrode of the write transistor is a storage node;
• the first word line is connected to the first gate, and the second word line is connected to the second gate;
• and
• the first bit line is connected to the first electrode of the storage transistor, and the second bit line is connected to both the second electrode of the storage transistor and the second electrode of the write transistor,
• wherein the first bit line is configured to:
• supply a first reference voltage to the first electrode of the storage transistor in a pre-charging stage, supply a data voltage of data to be written into the storage transistor in a data writing stage, and read data written into the memory node in response to whether the storage transistor is turned on in a data reading stage;
• and
• the second bit line is configured to:
• supply the first reference voltage to both the second electrode of the storage transistor and the second electrode of the write transistor in the pre-charging stage, be floated in the data writing stage, and supply a second reference voltage to both the storage transistor and the write transistor in the data reading stage,
• wherein the first reference voltage is greater than a sum of a maximum data voltage to be written into the memory cell and a threshold voltage of the storage transistor.