Data read-write circuit and method therefor, memory and driving method therefor, and electronic device

A circuit for reading and writing data, comprising:

• a memory cell, configured to store data, and comprising a capacitor, and a first transistor and a second transistor that are connected with a first electrode of the capacitor, wherein the capacitor further comprises a second electrode disposed opposite the first electrode, and an intersection point where the first electrode, the first transistor and the second transistor are connected with each other is a storage node of the memory cell;
• a data signal line, connected with the first transistor, and configured to:
• supply a first reference voltage to the first transistor in a standby stage and a precharging stage;
• supply a data voltage to the first transistor in a data writing stage;
• and read data in response to whether the first transistor is turned on in a data reading stage;
• and
• an auxiliary signal line, connected with the first transistor and the second transistor, and configured to:
• supply the first reference voltage to the first transistor in the standby stage and the precharging stage;
• be floated in the data writing stage;
• and simultaneously supply a second reference voltage to both the first transistor and the second transistor in the data reading stage;
• wherein a sum of a maximum data voltage corresponding to the data and a threshold voltage of the first transistor is a benchmark voltage, and the first reference voltage is greater than the benchmark voltage.

A memory, comprising:

• at least one memory cell, and at least one first bit line, at least one second bit line, at least one first word line, and at least one second word line that are correspondingly connected to the at least one memory cell;
• wherein each of the at least one memory cell comprises a capacitor, a first transistor, and a second transistor, the capacitor comprises a first electrode and a second electrode that are insulated, and each of the first transistor and the second transistor comprises a gate, a first terminal and a second terminal;
• the first electrode, the gate of the first transistor and the first terminal of the second transistor are connected with each other, and an intersection point where the first electrode, the gate of the first transistor and the first terminal of the second transistor are connected with each other is a storage node;
• the first word line is connected with the second electrode, and the second word line is connected with the gate of the second transistor;
• and
• the first bit line is connected with the first terminal of the first transistor, and the second bit line is connected to both the second terminal of the first transistor and the second terminal of the second transistor;
• wherein the first bit line is configured to:
• supply a first reference voltage to the first terminal of the first transistor in a precharging stage;
• supply a data voltage of data to be written to the first transistor in a data writing stage;
• and read data written into the storage node in response to whether the first transistor is turned on in a data reading stage;
• and
• the second bit line is configured to:
• supply simultaneously the first reference voltage to both the second terminal of the first transistor and the second terminal of the second transistor in the precharging stage;
• be floated in the data writing stage;
• and supply simultaneously a second reference voltage to both the first transistor and the second transistor in the data reading stage;
• wherein the first reference voltage is greater than a sum of a maximum data voltage to be written in the at least one memory cell and a threshold voltage of the first transistor.