Sense circuit for multi-transistor capacitorless dynamic random access memory (dram) cell

A dynamic random access memory (DRAM) integrated circuit (IC) memory chip, comprising:

• an array of capacitorless DRAM storage cells, each capacitorless DRAM storage cell coupled to one of multiple bitlines and one of multiple wordlines, each capacitorless DRAM storage cell including a first pair of series-coupled transistors that are activated during a read operation;
• reference cell circuitry including reference cells, each reference cell coupled to a separate one of the multiple bitlines;
• wherein for a given capacitorless DRAM storage cell activated during a read operation by a given wordline and bitline, a corresponding reference cell is coupled to the given bitline and cooperates with the given capacitorless DRAM storage cell to form a voltage divider circuit having a sense node;
• and
• sense amplifier circuitry, during the read operation, to sense a stored state of the given capacitorless DRAM storage cell based on a voltage developed by the voltage divider circuit at the sense node.

A method of operating a memory device, the method comprising:

• activating a capacitorless dynamic random access memory (DRAM) storage cell during a read operation;
• activating a reference cell that matches the capacitorless DRAM storage cell, the reference cell cooperating with the DRAM storage cell to form a voltage divider having a sense node;
• developing a voltage at the voltage divider sense node based on a stored state of the capacitorless DRAM storage cell;
• sensing the voltage developed by the voltage divider circuit;
• and
• amplifying the sensed voltage for presentation as a read data bit.