Row decoders having transistors placed in a plurality of rows and memory devices including the same

A row decoder, comprising:

• a first driving circuit including a first transistor among a first row of transistors, the first driving circuit being configured to generate a first driving signal onto a first wordline extending in a first direction;
• a second driving circuit including a second transistor among a second row of transistors, the second driving circuit being configured to generate a second driving signal onto a second wordline, the second wordline extending in the first direction and being adjacent to the first wordline in a second direction;
• wherein the first transistor and the second transistor functionally correspond to each other, and
• wherein the first row of transistors and the second row of transistors extend in the second direction and are arranged along the first direction.

A memory device, comprising:

• a first driving circuit including a first transistor among a first row of transistors, the first driving circuit being configured to provide a first driving signal to a first sub-wordline group via a first wordline extending in a first direction;
• and
• a second driving circuit including a second transistor among a second row of transistors, the second driving circuit being configured to provide a second driving signal to a second sub-wordline group via a second wordline, the second wordline extending in the first girection and being adjacent to the first wordline in a second direction,
• wherein the first transistor and the second transistor functionally correspond to each other, and
• wherein the first row of transistors and the second row of transistors extend in the second direction and are arranged along the first direction.