Semiconductor device

A semiconductor device, comprising:

• a first circuit block, configured to receive power from a first power supply region, and configured to operate according to a first clock signal, wherein the first circuit block comprises a multi-bit synchronizer and a register controller, the register controller comprises at least one first storage element, and the register controller is configured to output a write pulse signal to the multi-bit synchronizer;
• a second circuit block, configured to receive power from a second power supply region wherein the second circuit block comprises a clock gating cell and a data retention circuit, the clock gating cell is configured to selectively output a second clock signal according to a gating signal, and the data retention circuit is coupled to the multi-bit synchronizer;
• wherein, when the semiconductor device enters a power-saving mode, the first power supply region is powered off, and the second circuit block causes the clock gating cell to output the second clock signal according to a save enable signal;
• when the semiconductor device leaves the power-saving mode, the power supply in the first power supply region is restored;
• and
• when the save enable signal is at a second logic level, the second circuit block controls the clock gating cell to stop outputting the second clock signal;
• wherein, when power supply is restored to the data retention circuit after the first power supply region is powered off, a state value of an output signal of the first storage element before power-off is provided to the multi-bit synchronizer.