Display device

A display device, comprising:

• a plurality of pixels arrayed in a matrix including a plurality of pixel rows and a plurality of pixel columns;
• a plurality of scanning signal lines each associated with any of the plurality of pixel rows;
• a plurality of display signal lines each associated with any of the plurality of pixel columns;
• a scanning signal line driving circuit supplying the plurality of scanning signal lines with scanning signals each including a selection pulse selecting any of the plurality of pixel rows;
• a display signal line driving circuit supplying the plurality of display signal lines with display signals;
• and
• a control circuit supplying the scanning signal line driving circuit and the display signal line driving circuit with control signals,
• wherein the control circuit is configured to supply the scanning signal line driving circuit with k-phase gate clock signals (k is an integer of 4 or greater) having different phases from each other and gate start pulse signals,
• wherein the scanning signal line driving circuit includes a shift register circuit including a plurality of unit circuits,
• wherein each of the gate clock signals respectively input to the plurality of unit circuits has voltages of three levels of “L”, “Mid” and “H” (“L”<“Mid”<“H”), and rises in the order of “L” to “Mid” to “H”,
• wherein each of the gate start pulse signals respectively input to the plurality of unit circuits has voltages of three levels of “L”, “Mid” and “H” (“L”<“Mid”<“H”), and rises in the order of “L” to “Mid” to “H”, and
• wherein the timing at which the gate clock signals rise from “L” to “Mid” is between the timing at which the gate start pulse signals rise from “L” to “Mid” and the timing at which the gate start pulse signals rise from “Mid” to “H”.