Gate Driver and Display Device Including the Same

A gate driver, comprising:

• a control signal transfer part configured to generate a control signal based on a control clock signal and a carry signal;
• an inverted control signal transfer part configured to generate an inverted control signal based on the control clock signal and an inverted carry signal;
• a scan signal output part configured to generate a scan signal according to potentials of a first control node and a second control node that are charged or discharged according to a gate clock signal;
• and
• a scan signal selection part configured to selectively output the scan signal generated from the scan signal output part based on the control signal transmitted from the control signal transfer part,
• wherein the scan signal selection part includes a first transistor implemented as a p-channel thin film transistor (TFT) and a second transistor implemented as a p-channel TFT,
• wherein the first transistor includes a gate electrode to which the control signal is applied, a first electrode to which the scan signal is applied, and a second electrode connected to an output node, and
• wherein the second transistor includes a gate electrode to which the inverted control signal is applied, a first electrode connected to the output node, and a second electrode to which a low-potential voltage is applied.

A display device, comprising:

• a display panel on which a plurality of data lines are applied, a plurality of gate lines crossing the plurality of data lines are applied, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are disposed;
• a data driver configured to supply a data voltage of pixel data to the plurality of data lines;
• a gate driver configured to supply a gate signal to the plurality of gate lines;
• and
• a timing controller configured to control operation timings of the data driver and the gate driver,
• wherein the gate driver comprises:
• a control signal transfer part configured to generate a control signal based on a control clock signal and a carry signal;
• a scan signal output part configured to generate a scan signal according to potentials of a first control node and a second control node that are charged or discharged according to a gate clock signal;
• and
• a scan signal selection part configured to selectively output the scan signal generated from the scan signal output part based on the control signal transmitted from the control signal transfer part,
• wherein the scan signal selection part includes a first transistor implemented as a p-channel thin film transistor (TFT) and a second transistor implemented as an n-channel TFT,
• wherein the first transistor includes a gate electrode to which the control signal is applied, a first electrode to which the scan signal is applied, and a second electrode connected to an output node, and
• wherein the second transistor includes a gate electrode to which the control signal is applied, a first electrode to the output node, and a second electrode connected to which a low-potential voltage is applied.

A display device, comprising:

• a display panel on which a plurality of data lines are applied, a plurality of gate lines crossing the plurality of data lines are applied, a plurality of power lines to which different constant voltages are applied, and a plurality of sub-pixels are disposed;
• a data driver configured to supply a data voltage of pixel data to the plurality of data lines;
• a gate driver configured to supply a gate signal to the plurality of gate lines;
• and
• a timing controller configured to control operation timings of the data driver and the gate driver,
• wherein the gate driver includes:
• a control signal transfer part configured to generate a control signal based on a control clock signal and a carry signal;
• an inverted control signal transfer part configured to generate an inverted control signal based on the control clock signal and an inverted carry signal;
• a scan signal output part configured to generate a scan signal according to potentials of a first control node and a second control node that are charged or discharged according to a gate clock signal;
• and
• a scan signal selection part configured to selectively output the scan signal generated from the scan signal output part based on the control signal transmitted from the control signal transfer part,
• wherein the scan signal selection part includes a first transistor implemented as a p-channel thin film transistor (TFT) and a second transistor implemented as a p-channel TFT, and
• wherein the first transistor includes a gate electrode to which the control signal is applied, a first electrode to which the scan signal is applied, and a second electrode connected to an output node, and
• wherein the second transistor includes a gate electrode to which the inverted control signal is applied, a first electrode connected to the output node, and a second electrode to which a low-potential voltage is applied.