Semiconductor device having nanostructure transistor and methods of fabrication thereof

A semiconductor device structure, comprising:

• a first source/drain feature formed over a first device region of a substrate;
• a second source/drain feature formed over the first device region of the substrate;
• two or more first semiconductor layers disposed parallelly to each other and between the first source/drain feature and the second source/drain feature;
• a first gate electrode layer surrounding a portion of at least one of two or more first semiconductor layers;
• a first dielectric spacer disposed between two adjacent first semiconductor layers, the first dielectric spacer being in contact with the first source/drain feature;
• and
• a first cap layer surrounding an edge portion of at least one of the two or more first semiconductor layers.

A semiconductor device structure, comprising:

• a source/drain feature over a substrate;
• a plurality of semiconductor layers over the substrate;
• a gate electrode layer surrounding a portion of at least one of the plurality of semiconductor layers;
• a gate dielectric layer disposed between the gate electrode layer and the at least one of the plurality of semiconductor layers;
• a dielectric spacer disposed between two adjacent semiconductor layers of the plurality of semiconductor layers, the dielectric spacer being in contact with the source/drain feature;
• and
• a cap layer comprising:
• a first portion disposed between and in contact with the dielectric spacer and the gate dielectric layer;
• and
• a second portion extending from the first portion and disposed between and in contact with the dielectric spacer and one of the two adjacent semiconductor layers,
• wherein the gate electrode layer is separated from the dielectric spacer by the cap layer.