Compile time reduction and improved routability for circuit designs

A system, comprising:

• a hardware processor;
• and
• one or more computer-readable storage media storing program instructions to cause the hardware processor to perform operations comprising:
• generating, by a first machine learning model and prior to placement, a congestion prediction for a circuit design for an integrated circuit based on a plurality of first features of the circuit design;
• in response to the congestion prediction indicating congestion of the circuit design, generating N different implementation strategies for the circuit design;
• and
• placing and routing the circuit design using each of the N different implementation strategies.

A computer program product comprising:

• one or more computer-readable storage media;
• and
• program instructions stored on the one or more computer-readable storage media to perform operations comprising:
• generating, by a first machine learning model and prior to placement, a congestion prediction for a circuit design for an integrated circuit based on a plurality of first features of the circuit design;
• in response to the congestion prediction indicating congestion of the circuit design, generating N different implementation strategies for the circuit design;
• and
• placing and routing the circuit design using each of the N different implementation strategies.