High parallelism dpim
OwnerBalaji Vijayakumar, John Yu +1inventors
InventorsBALAJI VIJAYAKUMAR, JOHN YU, KRISHNAMURTHY SUBRAMANIAN
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Abstract
A digital processing-in-memory (DPIM) macro optimizes memory partitioning and compute parallelism. Ahead-of-cycle memory readout with simplified local storage, where the readout is held in a flip-flop for four or eight cycles to enable efficient processing. A pipelined adder tree implemented, with design optimizations to fully utilize the available bit-widths at each stage, ensuring efficient aggregation and processing of input bits. The DPIM efficiently processes 4-bit and 8-bit inputs with 1-bit weights over multiple cycles.
Claims19
(canceled)
A digital Processing-in-memory (DPIM) macro, comprising:
- two or more groups of DPIM slices, wherein each group has the same number of slices, and each slice has a same number of 6T bit-cell clusters, and
- a local bit-line, connected to each bit-cell in a cluster, and connected to a temporary storage device (D flip-flop) that is controlled to maintain a weight read out from one of the bit cells in each cluster ahead of a next compute cycle, wherein the weights are read out from each 6T bit-cell cluster comprising the two of more groups of DPIM slices in parallel.
A method for performing a DPIM macro compute operation, comprising:
- reading out weight information maintained by a selected bit-cell comprising each one of a plurality of 6T bit-cell clusters comprising each DPIM slice prior to a next compute phase;
- applying input vector information to the read out weights during a current compute phase;
- and
- the DPIM macro using the stored weight information and an input vector to perform MAC operations in each slice comprising the DPIM in parallel during a current compute phase.
Dependencies are inferred from the claim text.