Communication system with improved propagation delay and slave device thereof
AssigneePixart Imaging Inc.
InventorYEN-HSIANG CHEW
Life of this patent
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Abstract
There is provided a communication system including a master device and a slave device. The master device includes a first interface port and a second interface port. When the master device runs a read operation, the first interface port is used to output a serial clock to the slave device. The slave device includes a clock generator used to generate a delayed serial clock having the same phase as read data according to the serial clock. The second interface port is used to receive the delayed serial clock and the read data to eliminate a time delay in a data transaction.
Claims16
A communication system, comprising:
- a master device, comprising a first interface port and a second interface port;
- and
- a slave device, configured to
- receive a serial clock (SCLK) from the first interface port via a first SCLK line, and
- output a loopback SCLK to the second interface port via a second SCLK line,
- wherein a route propagation delay of the loopback SCLK matches a route propagation delay of read data to eliminate a clock propagation delay and a data propagation delay.
A slave device adopting an SPI, the slave device comprising:
- a first SCLK pin, configured to receive an SCLK;
- a second SCLK pin, configured to output a loopback SCLK;
- and
- a master-in-slave-out (MISO) pin, configured to output read data,
- wherein a route propagation delay of the loopback SCLK matches a route propagation delay of the read data to eliminate a clock propagation delay and a data propagation delay.
A communication system, comprising:
- a master device, comprising a first interface port and a second interface port;
- and
- a slave device, coupled to the first interface port via a first clock line from a first clock pin thereof, a slave select line and a MOSI line, and coupled to the second interface port via a second clock line from a second clock pin thereof and a MISO line, wherein
- the MISO line is configured to transmit read data from the slave device to the master device,
- the second clock pin is loopbacked from the first clock pin to output a loopback SCLK of an SCLK received by the first clock pin from the master device, and
- a route propagation delay of the loopback SCLK matches a route propagation delay of the read data to eliminate a clock propagation delay and a data propagation delay.
Dependencies are inferred from the claim text.