Cache data management in multicore systems
AssigneeAdvanced Micro Devices, Inc.
InventorPatrick J. Shyvers
Life of this patent
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Abstract
An implementation is a method for managing cache data in a multicore processor system includes detecting a request for exclusive access to a cacheline by a first processor core, granting exclusive access to the cacheline to the first processor core and invalidating copies of the cacheline in other processor cores, after the first processor core writes to the cacheline, copying the cacheline to a last level cache (LLC) when a number of invalidated copies of the cacheline exceeds a predetermined threshold, and servicing read requests for the cacheline from the LLC.
Claims20
A method for managing cache data in a multicore processor system, comprising:
- detecting a request for exclusive access to a cacheline by a first processor core;
- granting exclusive access to the cacheline to the first processor core and invalidating copies of the cacheline in other processor cores;
- after the first processor core writes to the cacheline, copying the cacheline to a last level cache (LLC) when a number of invalidated copies of the cacheline exceeds a predetermined threshold;
- and
- servicing read requests for the cacheline from the LLC.
A system for managing cache data, comprising:
- a plurality of processor cores, each processor having at least one associated cache;
- a last level cache (LLC) shared by the plurality of processor cores;
- and
- a cache management circuit configured to:
- detect when a first processor core of the plurality of processor cores obtains exclusive access to a cacheline and invalidates copies of the cacheline in other processor cores of the plurality of processor cores,
- after the first processor core performs a write to the cacheline, initiate a copy of the cacheline to the LLC when a number of invalidated copies of the cacheline exceeds a predetermined threshold, and
- service read requests for the cacheline from the LLC.
A system, comprising:
- a plurality of processor cores;
- a shared cache accessible by the plurality of processor cores;
- and
- a cache management circuit integrated configured to:
- detect when a first processor core of the plurality of processor cores obtains exclusive access to a cacheline after invalidating copies of the cacheline in at least a threshold number of other processor cores,
- copy the cacheline from the first processor core to the shared cache after the first processor core writes to the cacheline, and
- service read requests for the cacheline from the shared cache.
Dependencies are inferred from the claim text.