Merging Directory Updates for Reduced Latency

A processor comprising:

• a cache system having one or more cache levels;
• a directory to track cache line states in the cache system for one or more processor cores;
• and
• a cache controller communicatively coupled to the directory and configured to:
• receive, from a processor core of the one or more processor cores, a memory access request to a cache line in the cache system;
• send a self-invalidating lookup command to the directory, the self-invalidating lookup command causing the directory to perform a lookup operation to identify each processor core having a copy of the cache line and initiate one or more invalidation sequences for the processor core;
• and
• receive, from the directory, a response indicating results of the self-invalidating lookup command.

A method comprising:

• receiving, by a directory from a cache controller communicatively coupled to the directory, a self-invalidating lookup command caused by a request to update a cache line;
• performing a lookup operation to identify each processor core having a copy of the cache line;
• initiating an invalidation sequence for each processor core having the copy of the cache line;
• and
• updating cache line states in the directory to reflect invalidation of the cache line.