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US 2026/0300136 A1Published application
Auto-Compensating Pipeline Architecture
AssigneeQUALCOMM Incorporated
InventorsHimanshu ARORA, Tanya JHA, Maxwin Davis VALLULLY, Sreenath ARIYOOR KORATT, Kavya Sri GANGISHETTI
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Abstract
A system is provided with various trace destinations that timestamp data and/or instructions to provide timestamped information that is used by a debugging tool to debug the system. Each trace destination receives a timestamp from an auto-compensating propagation path that increments the timestamp responsive to the number of pipeline stages in the auto-compensating propagation path.
Claims20
A system comprising:
- a timer configured to increment a timestamp responsive to a clock signal;
- and
- a first propagation path coupled between the timer and a first trace destination and including a plurality of P first pipeline stages arranged in a series, wherein P is a plural positive integer, each first pipeline stage in the plurality of P first pipeline stages being configured to register the timestamp responsive to the clock signal, and wherein the first propagation path is configured to increment the timestamp to provide an incremented version of the timestamp that is incremented by P bits to the first trace destination.
A system, comprising:
- a timer configured to increment a timestamp responsive to a clock signal;
- and
- a first propagation path coupled between the timer and a first trace destination and including at least one incrementing pipeline stage that includes:
- a first start of frame register configured to register a start of frame bit responsive to the clock signal to provide a registered start of frame signal that is asserted to indicate a start of frame of the timestamp;
- a multiplexer configured to select for a binary one input bit responsive to an assertion of the registered start of frame signal to form a binary multiplexer output signal;
- an adder configured to add the timestamp with the binary multiplexer output signal to form a summed output bit;
- and
- a first timestamp register configured to register the summed output bit responsive to the clock signal to form an incremented timestamp.
5 more elements
A method of debugging a system, comprising:
- generating a timestamp in a counter responsive to a first cycle of a clock signal;
- shifting the timestamp through a plurality of P registers arranged in a series between the counter and a trace destination during P additional cycles of the clock signal following the first cycle, wherein P is a plural positive integer;
- and
- incrementing the timestamp by P during the shifting of the timestamp through the plurality of P registers so that the trace destination receives an incremented version of timestamp.
1 more element
Dependencies are inferred from the claim text.