System and method for implementing quires using a memory controller
AssigneeTactical Computing Laboratories, LLC
InventorMartin M. Deneroff
Life of this patent
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Abstract
Methods for performing posit processes using a quire implemented by a memory controller and corresponding systems and computer-readable mediums. A method performed by the memory controller can include receiving one or more quire operation commands from at least one processing core, executing the quire operation commands on a quire in a memory to produce an operation result, converting the operation result into a posit or floating-point result, and returning the result to one of the cores.
Claims20
A method for performing posit processes using a quire implemented by a memory controller, the method performed by the memory controller and comprising:
- receiving, by a memory controller, one or more quire operation commands from at least one processing core;
- executing the quire operation commands, by the memory controller, on a quire in a memory to produce an operation result;
- converting the operation result into a posit or floating-point result by the memory controller;
- and
- returning the result to one of the at least one processing core by the memory controller.
A quire memory controller comprising:
- a memory controller unit in communication with a memory;
- a communications crossbar configured to receive requests from a plurality of processing cores and to transmit responses to the plurality of processing cores;
- an issue/retry block in communication with the communications crossbar;
- a cache read stage in communication with the issue/retry block and an atomic cache;
- an operation steering stage in communication with the cache read stage, the memory controller unit, and the atomic cache;
- an adder pipeline in communication with the operation steering stage;
- a cache/memory update stage in communication with the adder pipeline, the memory controller unit, and the atomic cache;
- and
- a response unit in communication with the cache/memory update stage and the communications crossbar.
A computer system, comprising:
- a plurality of processing cores;
- an on-chip interconnect;
- and
- a quire memory controller connected to communicate with the plurality of processing cores and to control an external memory, wherein the quire memory controller implements at least one quire accessible by the plurality of processing cores and stored in the memory.
A quire memory controller comprising:
- a memory controller unit in communication with a memory;
- a communications crossbar configured to receive requests from a plurality of processing cores and to transmit responses to the plurality of processing cores;
- an issue/retry block in communication with the communications crossbar;
- a cache read stage in communication with the issue/retry block and an atomic cache;
- an operation steering stage in communication with the cache read stage, the memory controller unit, and the atomic cache;
- an adder pipeline in communication with the operation steering stage;
- a cache/memory update stage in communication with the adder pipeline, the memory controller unit, and the atomic cache;
- a response unit in communication with the cache/memory update stage and the communications crossbar;
- and
- a retry queue in communication with the operation steering stage and the issue/retry block,
- wherein the quire memory controller is configured to implement at least one quire stored at an address in the memory and accessible by the plurality of processing cores, and wherein the adder pipeline is configured to convert a received value from a posit or floating-point format to a quire format and to add the converted value to the quire.
Dependencies are inferred from the claim text.