Multipurpose multiply-accumulator array

The circuit of claim, wherein selection of operands from the one or more input memories is further controlled based on a data type.

The circuit of claim, wherein the operation type is in the set of:

• a three-dimensional convolution, a matrix multiplication, a depth-wise convolution, and an M×N filter operations, where M and N are integers.

The circuit of claim, wherein the one or more input memories comprise a first first-in first-out memory (FIFO) configured to receive a plurality of first operands and a second first-in first-out memory (FIFO) configured to receive a plurality of second operands, wherein the first operands and second operands are coupled to the plurality of multiply-accumulator circuits as pairs of operands.

The circuit of claim, further comprising a state machine having at least one input to receive a signal indicting an operation and/or data types and a plurality of FIFO memory outputs configured to control loading of operands into the plurality of multiply-accumulator circuits based on the operation and/or data types.

The circuit of claim, further comprising a plurality of read logic circuits, wherein each of the plurality of multiply-accumulator circuits has an associated read logic circuit to control loading of operands.

The circuit of claim, wherein each read logic circuit comprises a read pointer and a state machine to control reading of operands by the read pointer.

The circuit of claim, further comprising a plurality of identifiers configured to specify a position of each of the plurality of multiply-accumulator circuits within the multipurpose multiply-accumulator (MAC) array circuit so that the plurality of multiply-accumulator circuits independently receive and operate on operands from the one or more memories.

The circuit of claim, wherein the read logic circuits read and assign operands to each multiply-accumulator circuit based on the operation type being performed and the identifier.

The circuit of claim, wherein the plurality of multiply-accumulator circuits receive operands from the at least one input memory without software interaction.

The circuit of claim, wherein the operation type is a three-dimensional convolution, and wherein, during execution, each multiply-accumulator circuit in each column receives a unique first operand, and wherein each multiply-accumulator circuit in each row receives a unique second operand, and wherein the plurality of multiply-accumulator circuits produce results at different times.

The circuit of claim, wherein the operation type is a depth-wise convolution, and wherein, during execution, each multiply-accumulator circuit in each row receives a different first operand and each multiply-accumulator circuit in each column a different second operand, and wherein each multiply-accumulator circuit receives a unique channel number from the first and second operands.

The circuit of claim, wherein the operation type is an M×N filter operations, where M and N are integers, and wherein the multiply-accumulator (MAC) array circuit is partitioned into a plurality of groups, and wherein different groups received the same filter elements and process different operands along at least one dimension.

The circuit of claim, wherein the operation type is a matrix multiplication, and wherein each multiply-accumulator circuit receives a different column and different row of two input vectors.

The method of claim, wherein selection of operands from the one or more input memories is further controlled based on a data type.

The method of claim, wherein the operation type is in the set of:

• a three-dimensional convolution, a matrix multiplication, a depth-wise convolution, and an M×N filter operations, where M and N are integers.

The method of claim, wherein the one or more input memories comprise a first first-in first-out memory (FIFO) configured to receive a plurality of first operands and a second first-in first-out memory (FIFO) configured to receive a plurality of second operands, wherein the first operands and the second operands are coupled to the plurality of multiply-accumulator circuits as pairs of operands.

The method of claim, wherein the multiply-accumulator (MAC) array circuit comprises a state machine having at least one input to receive a signal indicting an operation and/or data type and a plurality of FIFO memory outputs configured to control loading of operands into the plurality of multiply-accumulator circuits based on the operation and/or data types.

The method of claim, wherein the multiply-accumulator (MAC) array circuit comprises a plurality of read logic circuits, wherein each of the plurality of multiply-accumulator circuits has an associated read logic circuit to control loading of operands.