Sgd refresh techniques for non-volatile memory

A memory device, comprising:

• a memory block that includes a plurality of drain-side select gate layers (SGDs) to be refreshed;
• and
• circuitry for refreshing the SGDs in a plurality of program loops of a refresh operation, the circuitry being configured during each program loop of the refresh operation to;
• apply a round of sequential programming pulses to the plurality of SGDs to increase threshold voltages of the memory cells in the plurality of SGDs, and
• after the round of sequential programming pulses is completed, perform a round of sequential verify operations on the plurality of SGDs to compare the threshold voltages of the memory cells in the plurality of SGDs to a verify level.

A computing system, comprising:

• a processing unit and a plurality of non-volatile memory packages in electrical communication with the processing unit;
• at least one of the non-volatile memory packages including a memory block that includes a plurality of drain-side select gate layers (SGDs) to be refreshed and including circuitry for refreshing the SGDs in a plurality of program loops of a refresh operation, the circuitry being configured during each program loop of the refresh operation to;
• apply a round of sequential programming pulses to the plurality of SGDs to increase threshold voltages of the memory cells in the plurality of SGDs, and
• after the round of sequential programming pulses is completed, perform a round of sequential verify operations on the plurality of SGDs to compare the threshold voltages of the memory cells in the plurality of SGDs to a verify level.