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US 2026/0299808 A1Published application
Memory device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsRyota WATANABE, Hidemitsu KOJIMA
Life of this patent
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Abstract
A memory device includes a first memory column, a memory array and a sign decoder. The first memory column is configured to store first sign bits. The memory array is configured to store a first data array and generate bit line signals. The sign decoder is configured to output data signals according to the first sign bits and the bit line signals. The data signals correspond to a second data array, and the first data array is generated by reversing rows of the second data array according to the first sign bits.
Claims20
A memory device, comprising:
- a first memory column configured to store a plurality of first sign bits;
- a memory array configured to store a first data array and generate a plurality of bit line signals;
- and
- a sign decoder configured to output a plurality of data signals according to the plurality of first sign bits and the plurality of bit line signals,
- wherein the plurality of data signals corresponds to a second data array, and
- the first data array is generated by reversing rows of the second data array according to the plurality of first sign bits.
3 more elements
A system, comprising:
- a processor configured to generate a plurality of sign bits according to a column quantity of a first data array and a row quantity of the first data array, and reverse rows of the first data array to generate a second data array;
- and
- a manufacturing device configured to manufacture a memory device storing the first data array and the plurality of sign bits,
- wherein the memory device is configured to output the first data array.
1 more element
A system, comprising:
- a processor configured to generate a first vector according to logic values in a first data array, updating a second vector based on the first vector, and reverse rows of the first data array according to the second vector being updated, to generate a second data array;
- and
- a memory device configured to store the second data array.
Dependencies are inferred from the claim text.