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US 2026/0299788 A1Published application
Memory write command configuration for accelerated execution
AssigneeMicron Technology, Inc.
InventorLuca Bert
Life of this patent
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Abstract
Systems, methods, and apparatus related to commands for accessing storage spaces of memory systems (e.g., solid-state drive (SSD) having NAND flash memory). A host system sends write commands to the memory systems. The write commands can include normal commands according to a current NVMe standard and fast commands extending the NVMe standard. The memory systems can tell whether a write command is a normal command or a fast command based on the opcode embedded in the command.
Claims20
A memory sub-system comprising:
- non-volatile memory;
- and
- at least one controller configured to:
- retrieve a first write command, wherein the first write command includes a first opcode configured to cause the controller to transfer first data from a memory location identified via the first write command to the non-volatile memory, and the first opcode has a value of 0x01;
- execute the first write command to transfer the first data;
- retrieve a second write command, wherein the second write command includes a second opcode different from the first opcode, and the second opcode is configured to cause the controller to transfer second data from a memory location identified via the second write command to the non-volatile memory;
- and
- execute the second write command to transfer the second data.
5 more elements
A memory sub-system, comprising:
- non-volatile memory;
- and
- a controller configured to:
- retrieve a first command, the command including:
- a first opcode configured to cause the controller to write data to the non-volatile memory;
- a logical block addressing (LBA) address identifying a block in a logical storage space partitioned into a plurality of logical blocks of a common size;
- and
- a memory address in random access memory;
- and
- execute the first command to retrieve the data from the random access memory according to the memory address, allocate a portion of the non-volatile memory to implement the block represented by the logical block addressing (LBA) address, and program the portion of the non-volatile memory to have states representative of the data;
- wherein the first opcode is different from a second opcode according to a standard for non-volatile memory express (NVMe);
- wherein when the first opcode in the first command is replaced with the second opcode to generate a second command, the second command includes a plurality of bit segments configured to provide parameters according to the standard for non-volatile memory express (NVMe) to write the data to the logical block address;
- and
- wherein the controller is configured to, in response to the first opcode being specified in the first command, skip processing of the plurality of bit segments in execution of the first command.
11 more elements
A memory sub-system, comprising:
- non-volatile memory;
- and
- a controller configured to:
- retrieve a first command from a submission queue, the command including:
- a first opcode configured to cause the controller to write data to the non-volatile memory;
- a logical block addressing (LBA) address identifying a block in a logical storage space partitioned into a plurality of logical blocks of a common size;
- and
- a memory address in random access memory;
- and
- execute the first command to retrieve the data from the random access memory according to the memory address, allocate a portion of the non-volatile memory to implement the block represented by the logical block addressing (LBA) address, and program the portion of the non-volatile memory to have states representative of the data;
- wherein the first opcode is different from a second opcode according to a standard for non-volatile memory express (NVMe);
- wherein when the first opcode in the first command is replaced with the second opcode to generate a second command, the second command includes a plurality of bit segments configured to provide parameters according to the standard for non-volatile memory express (NVMe) to write the data to the logical block address;
- and
- wherein the controller is configured to, in response to the first opcode being specified in the first command, skip processing of the plurality of bit segments in execution of the first command.
11 more elements
Dependencies are inferred from the claim text.