Back to results
US 2026/0299787 A1Published application
Memory read command configuration for accelerated execution
AssigneeMicron Technology, Inc.
InventorLuca Bert
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatus related to commands for accessing storage spaces of memory systems (e.g., solid-state drive (SSD) having NAND flash memory). A host system sends read commands to the memory systems. The read commands can include normal commands according to a current NVMe standard and fast commands extending the NVMe standard. The memory systems can tell whether a read command is a normal command or a fast command based on the opcode embedded in the command.
Claims20
A memory sub-system comprising:
- non-volatile memory;
- and
- at least one controller configured to:
- retrieve a first read command, wherein the first read command includes a first opcode configured to cause the controller to transfer first data to a memory location identified via the first read command from the non-volatile memory, and the first opcode has a value of 0x02;
- execute the first read command to transfer the first data;
- retrieve a second read command, wherein the second read command includes a second opcode different from the first opcode, and the second opcode is configured to cause the controller to transfer second data to a memory location identified via the second read command from the non-volatile memory;
- and
- execute the second read command to transfer the second data.
5 more elements
A memory sub-system, comprising:
- non-volatile memory;
- and
- a controller configured to:
- retrieve a first command, the command including:
- a first opcode configured to cause the controller to read data from the non-volatile memory;
- a logical block addressing (LBA) address identifying a block in a logical storage space partitioned into a plurality of logical blocks of a common size;
- and
- a memory address in random access memory;
- and
- execute the first command to transfer the data from the block to the random access memory according to the memory address;
- wherein the first opcode is different from a second opcode according to a standard for non-volatile memory express (NVMe);
- wherein when the first opcode in the first command is replaced with the second opcode to generate a second command, the second command includes a plurality of bit segments configured to provide parameters according to the standard for non-volatile memory express (NVMe) to read the data from the logical block address;
- and
- wherein the controller is configured to, in response to the first opcode being specified in the first command, skip processing of the plurality of bit segments in execution of the first command.
11 more elements
A memory sub-system, comprising:
- non-volatile memory;
- and
- a controller configured to:
- retrieve a first command from a submission queue, the command including:
- a first opcode configured to cause the controller to read data from the non-volatile memory;
- a logical block addressing (LBA) address identifying a block in a logical storage space partitioned into a plurality of logical blocks of a common size;
- and
- a memory address in random access memory;
- and
- execute the first command to retrieve the data from a portion of the non-volatile memory allocated to implement the block represented by the logical block addressing (LBA) address, and store the data to the random access memory according to the memory address;
- wherein the first opcode is different from a second opcode according to a standard for non-volatile memory express (NVMe);
- wherein when the first opcode in the first command is replaced with the second opcode to generate a second command, the second command includes a plurality of bit segments configured to provide parameters according to the standard for non-volatile memory express (NVMe) to read the data from the logical block address;
- and
- wherein the controller is configured to, in response to the first opcode being specified in the first command, skip processing of the plurality of bit segments in execution of the first command.
11 more elements
Dependencies are inferred from the claim text.