System and Method for Partial Memory Integrity

A device comprising:

• a processor core;
• a wireless transmitter coupled to the processor core;
• and
• a memory, coupled to the processor core, wherein the memory is configured to:
• configure a contiguous address space of the memory for read and write operations and for storing memory integrity data, including designating N memory regions for the read and write operations;
• and
• enable memory integrity operations on M of the N memory regions, where N is an integer greater than one, and M is an integer less than N and greater than zero,
• wherein the processor core is configured to:
• request an access to the user data stored in the memory;
• and
• generate an indication based on the user data, and
• wherein the wireless transmitter is configured to:
• transmit a signal based on the indication.

A method comprising:

• configuring, in a memory having a first set of memory regions and a second set of memory regions, the first set of memory regions to store user data;
• and
• configuring the second set of memory regions to store the user data or integrity data indicative of an integrity status of the user data, which includes:
• disabling a memory integrity operation for a first memory region of the second set of memory regions, such that the first memory region is configured to store the user data instead of the integrity data;
• and
• enabling the memory integrity operation for a remainder of the second set of memory regions, such that the remainder of the second set of memory regions is configured to store the integrity data instead of the user data.