Processor-based system employing configurable local frequency throttling management to manage power demand and consumption, and related methods

A system comprising:

• a processing unit configured to execute program code at a rate based on a current frequency of a clock signal;
• a clock control circuit configured to generate the clock signal at the current frequency on a clock output;
• wherein the clock control circuit is configured to:
• in response to receiving a frequency throttle signal:
• generate the clock signal on the clock output at an intermediate frequency between the current frequency and a throttle frequency lower than the current frequency;
• in response to verifying the clock signal at the intermediate frequency, generate the clock signal on the clock output at the throttle frequency;
• and
• communicate a frequency throttle completion signal indicating the clock signal at the throttle frequency;
• and
• a power control circuit configured to:
• in response to receiving the frequency throttle completion signal, set a current operating voltage of a power signal to a higher operating voltage that is higher than the current operating voltage of the power signal.

A method comprising:

• receiving a frequency throttle signal at a clock control circuit configured to generate a clock signal at a current frequency on a clock output;
• generating the clock signal on the clock output at an intermediate frequency between the current frequency and a throttle frequency lower than the current frequency;
• in response to verifying the clock signal at the intermediate frequency, generating the clock signal on the clock output at the throttle frequency;
• and
• communicating a frequency throttle completion signal indicating the clock signal at the throttle frequency;
• and
• in response to the frequency throttle completion signal, setting a first operating voltage of a power signal to a second operating voltage that is higher than the first operating voltage.

A system-on-a-chip comprising:

• a processing unit configured to execute program code at a rate based on a current frequency of a clock signal;
• a clock control circuit configured to generate the clock signal at the current frequency on a clock output;
• wherein the clock control circuit is configured to:
• in response to receiving a frequency throttle signal:
• generate the clock signal on the clock output at an intermediate frequency between the current frequency and a throttle frequency that is lower than the current frequency;
• in response to verifying the clock signal at the intermediate frequency, generate the clock signal on the clock output at the throttle frequency;
• and
• communicate a frequency throttle completion signal indicating the clock signal at the throttle frequency;
• and
• a power control circuit configured to:
• in response to receiving the frequency throttle completion signal, set a current operating voltage of a power signal for the system-on-a-chip to a higher operating voltage that is higher than the current operating voltage of the power signal.