Performance state aware dynamic clock gating

A method comprising:

• determining, using a power management circuit, a workload demand for a processor circuit having a plurality of circuit blocks;
• changing, in response to determining that the workload demand is less than a threshold level, a performance state of the processor circuit from a first one of a plurality of performance states to a second one of the plurality of performance states, wherein a power consumption of the processor circuit operating in the second one of the plurality of performance states is less than the power consumption of the processor circuit operating in the first one of the plurality of performance states;
• and
• activating, using the power management circuit, a first operational mode in at least one circuit block of the plurality of circuit blocks, wherein the first operational mode is based on a timing margin associated with the second one of the plurality of performance states.

A system comprising:

• a processor circuit having a plurality of circuit blocks;
• a power management circuit configured to determine a respective one of a plurality of performance states in which ones of the plurality of circuit blocks is to operate based on respectively determined workloads for ones of the plurality of circuit blocks, and wherein the power management circuit is further configured to, in response to determining that a workload demand for at least one circuit block of the plurality of circuit blocks is less than a threshold level:
• change, for the at least one circuit block of the plurality of circuit blocks, operation from a first performance state having a first clock frequency to a second performance state having a second clock frequency less than the first clock frequency;
• and
• activate, based on timing margins associated with the second clock frequency, a clock-gating mode in the at least one circuit block of the plurality of circuit blocks.