Wafer-level intelligent photonic computing chip system and architecture

A computing method based on a wafer-level intelligent photonic computing chip system, comprising:

• obtaining an input matrix to be computed, and obtaining a first encoded vector by performing multi-path information channel encoding and compression on the input matrix;
• obtaining a second encoded vector by performing multi-path information reconfigurable computation weight on the input matrix;
• obtaining a feature vector by performing universal feature computation on the first encoded vector and the second encoded vector;
• obtaining a first decoded vector by performing first decoding representation on the feature vector;
• obtaining a second decoded vector by performing second decoding representation on the feature vector;
• and
• obtaining a target computation result by synthesizing the first decoded vector and the second decoded vector.

A non-transiency computer storage medium, storing computer executable instructions which, when executed by a processor, cause a computing method based on a wafer-level intelligent photonic computing chip system to be implemented, wherein the method comprises:

• obtaining an input matrix to be computed, and obtaining a first encoded vector by performing multi-path information channel encoding and compression on the input matrix;
• obtaining a second encoded vector by performing multi-path information reconfigurable computation weight on the input matrix;
• obtaining a feature vector by performing universal feature computation on the first encoded vector and the second encoded vector;
• obtaining a first decoded vector by performing first decoding representation on the feature vector;
• obtaining a second decoded vector by performing second decoding representation on the feature vector;
• and
• obtaining a target computation result by synthesizing the first decoded vector and the second decoded vector.