High-speed metasurface programming system

Abstract

Various embodiments of systems and methods are described for high-speed metasurface programming, especially for use in optical computing. The system enables precise voltage control over a large-scale metasurface matrix using an array of digital-to-analog converters (DACs) for programming discrete metasurface cells. A row driver array generates row-enable signals for row-by-row programming. A pixel sampler matrix includes switches and capacitors to perform sample-and-hold operations to maintain voltage levels with reduced refresh rate requirements. A common mode voltage switching circuit may be used to attain a zero average DC voltage across metasurface cells to reduce or minimize charge leakage. A leakage-reducing switch driver may drive subthreshold biasing to minimize transmission gate leakage. Independently controlled regions or quadrants may be used to reduce parasitic capacitance and/or enhance signal integrity.

Dependencies are inferred from the claim text.