Clock synchronization circuit

An integrated circuit comprising:

• a communication interface;
• a controllable clock source having a frequency control input and a clock output;
• a counter having a clock input and a count output, the clock input coupled to the clock output;
• a command generation circuit having a phase input and a command output, the phase input coupled to the count output, and the command output coupled to the communication interface;
• a command processing circuit having a command input, and a reference phase output, the command input coupled to the communication interface;
• and
• a clock synchronization circuit having a clock correction output coupled to the frequency control input, the clock synchronization circuit including:
• a phase difference circuit having a reference phase input coupled to the reference phase output, a target phase input coupled to the count output, and a phase difference output;
• a phase correction circuit having an input coupled to the phase difference output, and a phase correction output coupled to the clock correction output;
• and
• a frequency correction circuit having an input coupled to the phase difference output, and a frequency correction output coupled to the clock correction output.

A system comprising:

• a Device Under Test (DUT) monitoring device including:
• a stimulus generation circuit having a stimulus output;
• an impedance spectroscopy circuit having a first spectroscopy input, a second spectroscopy input, and an impedance spectroscopy output;
• a current sense circuit having a current sense output;
• a first measurement device including:
• a reference clock source having a reference clock output;
• a counter having a first clock input and a count output, the first clock input coupled to the reference clock output;
• a synchronization command generation circuit having a phase input, and a command output, the phase input coupled to the count output;
• a first sampling circuit having a current sense input, a first sample output, and a second clock input, the second clock input coupled to the reference clock output, the current sense input coupled to the current sense output, and the first sampling circuit configured to receive a current measurement signal at the current sense input and provide samples of the current measurement signal at the first sample output;
• and
• a first processing circuit having a first processing input and a first processing output, the first processing input coupled to the first sample output, the first processing output coupled to the first spectroscopy input, and the first processing circuit configured to provide first signals representing spectral components of the current measurement signal at the first processing output;
• and
• a second measurement device including:
• a synchronization command processing circuit having a command input coupled to the command output, and a reference phase output, the synchronization command processing circuit configured to provide a reference count value at the reference phase output;
• a controllable clock source having a frequency control input and a first clock output, the controllable clock source configured to generate a clock signal;
• a clock synchronization circuit coupled to the synchronization command processing circuit, the clock synchronization circuit having a clock correction output coupled to the frequency control input, the clock synchronization circuit configured to generate a clock control signal that controls a frequency of the clock signal based on the reference count value, and controls a phase of the clock signal based on the reference count value;
• a second sampling circuit having a DUT input, a second sample output, and a third clock input, the third clock input coupled to the first clock output, and the second sampling circuit configured to receive a voltage measurement signal at the DUT input and provide samples of the voltage measurement signal at the second sample output;
• and
• a second processing circuit having a second processing input and a second processing output, the second processing input coupled to the second sample output, the second processing output coupled to the second spectroscopy input, and the second processing circuit configured to provide second signals representing spectral components of the voltage measurement signal at the second processing output.

A method comprising:

• generating, by a first device, a reference clock signal;
• providing, by the first device, a reference count value based on counting cycles of the reference clock signal;
• providing, by the first device, a command including the reference count value;
• receiving, by a second device, the command;
• generating, by the second device, a target clock signal;
• determining, by the second device, a target count value based on the target clock signal;
• and
• adjusting, by the second device, a frequency and a phase of the target clock signal based on a difference between the reference count value and the target count value.