Back to results
US 2026/0299019 A1Published application
Voltage contrast for backside processes on wafers
AssigneeIntel Corporation
InventorsPeter O'BRIEN, Joshua YABLON, Bradley R. YATES, Xiao WEN, Mark KOEPER, Mandip SIBAKOTI, Michael SPRINKLE, Trenton EDWARDS
Life of this patent
Estimating the term…
Abstract
Test devices and methods for performing voltage contrast inspections on semiconductor device backside metallization regions are provided. Test devices can include a semiconductor device layer and a virtual ground layer.
Claims20
A device comprising:
- a substrate;
- a virtual ground layer comprising a metallic layer and a semiconductor layer;
- a first metallization layer wherein the virtual ground layer is between the substrate and the first metallization layer and wherein the first metallization layer comprises dielectric layers and conductive lines and vias in the dielectric layers;
- and
- a device layer comprising semiconductor devices wherein the device layer is on the first metallization layer.
2 more elements
A method comprising:
- forming a backside metallization region on a surface of a test device, wherein the backside metallization region includes conductive regions and dielectric regions;
- wherein the test device comprises:
- a substrate;
- a virtual ground layer comprising a metallic layer and a semiconductor layer;
- a frontside metallization layer wherein the virtual ground layer is between the substrate and the frontside metallization layer and wherein the frontside metallization layer comprises dielectric layers and conductive lines and vias in the dielectric layers;
- and
- a device layer comprising semiconductor devices;
- and
- performing a voltage contrast inspection of the metallization region wherein the voltage contrast inspection allows determination of operability of conductive regions in the metallization region.
6 more elements
At least one machine-readable storage medium comprising non-transitory instructions, that when executed by a processor, cause a system to:
- form a backside metallization region on a surface of a test device, wherein the backside metallization region includes conductive regions and dielectric regions;
- wherein the test device comprises:
- a substrate;
- a virtual ground layer comprising a metallic layer and a semiconductor layer;
- a frontside metallization layer wherein the virtual ground layer is between the substrate and the frontside metallization layer and wherein the frontside metallization layer comprises dielectric layers and conductive lines and vias in the dielectric layers;
- and
- a device layer comprising semiconductor devices;
- and
- perform a voltage contrast inspection of the metallization region wherein the voltage contrast inspection allows determination of operability of conductive regions in the metallization region.
6 more elements
Dependencies are inferred from the claim text.