Liner for batch semiconductor processing apparatus

Abstract

A liner for a process chamber of a batch semiconductor processing apparatus is disclosed. The liner comprises a closed upper end; an open lower end adapted for receiving a substrate boat; and a plurality of exhaust openings in the liner, distributed between the upper end and the lower end. The liner has a first diameter in a first liner section adjacent to the upper end and a second diameter in a second liner section adjacent to the lower end. The liner diameter increases continuously from the first diameter to the second diameter in a transition section between the first section and the second section.

Dependencies are inferred from the claim text.