Semiconductor package with semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsYeongkwon Ko, Unbyoung Kang, Soyeon Kwon, Chungsun Lee
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Abstract
Provided is a semiconductor package including a first semiconductor device including a first semiconductor substrate, a first interconnect structure on the first semiconductor substrate, and a trench extending into the first interconnect structure and a portion of the first semiconductor substrate, a second semiconductor device on the first semiconductor device, and a cover insulating layer on the first semiconductor device and a side surface of the second semiconductor device, the cover insulating layer including a first portion filling the trench included in the first semiconductor device and contacting the first semiconductor substrate.
Claims20
A method of manufacturing a semiconductor package, the method comprising:
- providing a wafer-level structure comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate;
- forming a trench in the wafer-level structure, the trench extending into the first interconnect structure and a portion of the first semiconductor substrate;
- bonding a second semiconductor device to the wafer-level structure;
- and
- forming a cover insulating layer on the wafer-level structure and on a side surface of the second semiconductor device,
- wherein the forming of the cover insulating layer comprises filling the trench with a first portion of the cover insulating layer, and
- wherein the first portion of the cover insulating layer contacts the first semiconductor substrate.
A method of manufacturing a semiconductor package, the method comprising:
- providing a wafer-level structure comprising a first semiconductor substrate;
- bonding a second semiconductor device to the wafer-level structure;
- forming a cover insulating layer on the wafer-level structure and on a side surface of the second semiconductor device;
- forming a preliminary groove in an upper surface of the cover insulating layer, the preliminary groove overlapping a scribe lane of the wafer-level structure in a vertical direction;
- and
- singulating the wafer-level structure along the scribe lane to form a semiconductor package,
- wherein the semiconductor package comprises a groove formed from the preliminary groove in an edge portion of an upper surface of the cover insulating layer.
A method of manufacturing a semiconductor package, the method comprising:
- providing a wafer-level structure comprising a first semiconductor substrate and a first interconnect structure on the first semiconductor substrate;
- forming a trench in the wafer-level structure, the trench extending into the first interconnect structure and a portion of the first semiconductor substrate;
- bonding a second semiconductor device to the wafer-level structure;
- forming a cover insulating layer on the wafer-level structure and on a side surface of the second semiconductor device, the forming of the cover insulating layer comprising filling the trench with a first portion of the cover insulating layer;
- forming a preliminary groove in an upper surface of the cover insulating layer, the preliminary groove overlapping a scribe lane of the wafer-level structure in a vertical direction;
- and
- singulating the wafer-level structure along the scribe lane to form the semiconductor package,
- wherein the first portion of the cover insulating layer contacts the first semiconductor substrate, and
- wherein the semiconductor package comprises a groove formed from the preliminary groove in an edge portion of the upper surface of the cover insulating layer.
Dependencies are inferred from the claim text.