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US 2026/0293374 A1Published application
Light-emitting display device and electronic device including the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsRyo ARASAWA, Hideaki SHISHIDO
Life of this patent
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Abstract
An object is to provide a light-emitting display device in which a pixel including a thin film transistor using an oxide semiconductor has a high aperture ratio. The light-emitting display device includes a plurality of pixels each including a thin film transistor and a light-emitting element. The pixel is electrically connected to a first wiring functioning as a scan line. The thin film transistor includes an oxide semiconductor layer over the first wiring with a gate insulating film therebetween. The oxide semiconductor layer is extended beyond the edge of a region where the first wiring is provided. The light-emitting element and the oxide semiconductor layer overlap with each other.
Claims16
(canceled)
A light-emitting display device comprising:
- a first wiring configured to be a scan line, extended in a first direction in plan view;
- a second wiring configured to be a signal line, extended in a second direction crossing the first direction in plan view;
- a third wiring configured to be a power supply line, extended in the second direction in plan view;
- a first light-emitting element included in a first pixel;
- a first transistor included in the first pixel;
- a second transistor included in the first pixel;
- a second light-emitting element included in a second pixel adjacent to the first pixel;
- and
- a partition including a first opening overlapping the first light-emitting element and a second opening overlapping the second light-emitting element,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
- wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
- wherein a gate of the first transistor is electrically connected to the first wiring,
- wherein one of a source and a drain of the second transistor is electrically connected to the first light-emitting element,
- wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
- wherein a first oxide semiconductor layer including a channel formation region of the first transistor overlaps the second opening in plan view,
- wherein a channel length direction of the first transistor is in the first direction,
- wherein a channel length direction of the second transistor is in the second direction,
- wherein a channel length of the second transistor is larger than a channel length of the first transistor,
- wherein the first opening has a first portion with a first width in the first direction, a second portion with a second width in the first direction, and a third portion with a third width in the first direction in plan view,
- wherein the second width is smaller than the first width and the third width, and
- wherein in plan view, the first portion, the second portion, and the third portion are arranged in the second direction in this order.
18 more elements
A light-emitting display device comprising:
- a first wiring configured to be a scan line, extended in a first direction in plan view;
- a second wiring configured to be a signal line, extended in a second direction crossing the first direction in plan view;
- a third wiring configured to be a power supply line, extended in the second direction in plan view;
- a first light-emitting element included in a first pixel;
- a first transistor included in the first pixel;
- a second transistor included in the first pixel;
- a second light-emitting element included in a second pixel adjacent to the first pixel;
- and
- a partition including a first opening overlapping the first light-emitting element and a second opening overlapping the second light-emitting element,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
- wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
- wherein a gate of the first transistor is electrically connected to the first wiring,
- wherein one of a source and a drain of the second transistor is electrically connected to the first light-emitting element,
- wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
- wherein a first oxide semiconductor layer including a channel formation region of the first transistor overlaps the second opening in plan view,
- wherein a channel length direction of the first transistor is in the first direction,
- wherein a channel length direction of the second transistor is in the second direction,
- wherein a channel length of the second transistor is larger than a channel length of the first transistor,
- wherein the first opening has a first portion with a first width in the first direction, a second portion with a second width in the first direction, and a third portion with a third width in the first direction in plan view,
- wherein the second width is smaller than the first width and the third width,
- wherein in plan view, the first portion, the second portion, and the third portion are arranged in the second direction in this order, and
- wherein in plan view, an area where a first conductive layer configured to be the one of the source and the drain of the second transistor is in contact with a first electrode of the first light-emitting element is arranged with the second portion with the second width in the first direction.
19 more elements
A light-emitting display device comprising:
- a first wiring configured to be a scan line, extended in a first direction in plan view;
- a second wiring configured to be a signal line, extended in a second direction crossing the first direction in plan view;
- a third wiring configured to be a power supply line, extended in the second direction in plan view;
- a first light-emitting element included in a first pixel;
- a first transistor included in the first pixel;
- a second transistor included in the first pixel;
- a second light-emitting element included in a second pixel adjacent to the first pixel;
- and
- a partition including a first opening overlapping the first light-emitting element and a second opening overlapping the second light-emitting element,
- wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor,
- wherein the other of the source and the drain of the first transistor is electrically connected to the second wiring,
- wherein a gate of the first transistor is electrically connected to the first wiring,
- wherein one of a source and a drain of the second transistor is electrically connected to the first light-emitting element,
- wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
- wherein a first oxide semiconductor layer including a channel formation region of the first transistor overlaps the second opening in plan view,
- wherein a channel length direction of the first transistor is in the first direction,
- wherein a channel length direction of the second transistor is in the second direction,
- wherein a channel length of the second transistor is larger than a channel length of the first transistor,
- wherein the first opening has a first portion with a first width in the first direction, a second portion with a second width in the first direction, and a third portion with a third width in the first direction in plan view,
- wherein the second width is smaller than the first width and the third width,
- wherein in plan view, the first portion, the second portion, and the third portion are arranged in the second direction in this order,
- wherein in plan view, an area where a first conductive layer configured to be the one of the source and the drain of the second transistor is in contact with a first electrode of the first light-emitting element is arranged with the second portion with the second width in the first direction,
- wherein in plan view, a second conductive layer configured to be the gate of the second transistor has a first area with a fourth width in the first direction, a second area with a fifth width in the first direction, and a third area with a sixth width in the first direction,
- wherein the fifth width is smaller than the fourth width and the sixth width,
- wherein in plan view, the first area, the second area, and the third area are arranged in the second direction in this order, and
- wherein the second area is configured to be the gate of the second transistor.
23 more elements
Dependencies are inferred from the claim text.