Semiconductor Structure and Manufacturing Method Thereof

A method comprising:

• forming an epitaxial layer on a substrate, the epitaxial layer comprising a first lightly doped region extending from a top surface of the epitaxial layer toward the substrate;
• forming a trench extending from a top surface of the first lightly doped region into the epitaxial layer;
• forming, in the trench, a first polysilicon structure and a gate oxide layer surrounding the first polysilicon structure;
• forming an insulating layer on the first polysilicon structure and the gate oxide layer in the trench, and on the top surface of the first lightly doped region;
• forming a polysilicon layer disposed on the insulating layer into a second polysilicon structure in the trench and a third polysilicon structure over the top surface of the first lightly doped region simultaneously;
• forming the third polysilicon structure into a plurality of first doped regions of a first conductivity type and a plurality of second doped regions of a second conductivity type, the plurality of first doped regions and the plurality of second doped regions being alternately arranged and forming a diode string;
• and
• forming a source electrode over the first lightly doped region and adjoining the second polysilicon structure.

A semiconductor structure comprising:

• a substrate;
• an epitaxial layer on the substrate;
• a doped region in the epitaxial layer, the doped region extending from a top surface of the epitaxial layer toward the substrate;
• a diode string over the doped region, the diode string comprising a plurality of first doped regions and a plurality of second doped regions alternately arranged;
• and
• a gate structure, extending from a top surface of the doped region into the epitaxial layer, the gate structure comprising:
• a first polysilicon structure;
• a gate oxide layer surrounding the first polysilicon structure;
• a second polysilicon structure over the first polysilicon structure and the gate oxide layer, a top surface of the second polysilicon structure being coplanar with the top surface of the doped region;
• an insulating layer, comprising:
• a first portion disposed between the second polysilicon structure and the first polysilicon structure, in contact with the gate oxide layer, and surrounding the second polysilicon structure, and
• a second portion extending between the top surface of the doped region and the diode string;
• and
• a thermal oxide layer comprising:
• a first portion on the first polysilicon structure between the first polysilicon structure and the second polysilicon structure,
• a second portion on sidewalls of the gate structure, the second portion not in contact with the first portion of the thermal oxide layer, and
• a third portion between the top surface of the doped region and the second portion of the insulating layer.