Integrated circuit including standard cell and method of fabricating the same

An integrated circuit comprising:

• standard cells arranged over a plurality of rows, wherein the standard cells comprise:
• a plurality of functional cells each implemented as a logic circuit;
• and
• a plurality of filler cells comprising at least one density supplementary filler cell that comprises at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern,
• wherein the at least one density supplementary filler cell is configured to satisfy a density rule of any one of the at least one pattern in the integrated circuit, and
• wherein, to satisfy a density rule for metal cuts, the at least one density supplementary filler cell is pre-arranged before the plurality of functional cells are arranged.

A computing system for designing an integrated circuit, the computing system comprising:

• one or more processors;
• and
• a memory storing instructions that, when executed by the one or more processors, cause the one or more processors to:
• refer to a standard cell library comprising data defining a plurality of filler cells;
• arrange at least one density supplementary filler cell from among the plurality of filler cells to satisfy a density rule for metal cuts before arranging a plurality of functional cells;
• arrange the plurality of functional cells;
• route standard cells including the plurality of functional cells and the at least one density supplementary filler cell;
• and
• generate layout data based on the routed standard cells,
• wherein the at least one density supplementary filler cell comprises at least one pattern from among a back end of line (BEOL) pattern, a middle of line (MOL) pattern, and a front end of line (FEOL) pattern.