Semiconductor structure and method for forming the same

A method of forming a semiconductor structure, comprising:

• forming an n-type well region in a substrate;
• forming a first active region and a second active region over the n-type well region and extending in a first direction, wherein the first active region comprises first semiconductor layers arranged in a vertical direction and the second active region comprises second semiconductor layers arranged in the vertical direction;
• forming a first dummy gate extending in a second direction and across the first active region and the second active region, wherein the second direction is different from the first direction;
• forming a first source/drain feature and a second source/drain feature in the first active region and on opposite sides of the first dummy gate in the first direction, wherein each of the first source/drain feature and the second source/drain feature is attached to the first semiconductor layers and comprises a first bottom dielectric layer and a first doped epitaxial layer over the first bottom dielectric layer;
• forming a third source/drain feature and a fourth source/drain feature in the second active region and on the opposite sides of the first dummy gate, wherein each of the third source/drain feature and the fourth source/drain feature is attached to the second semiconductor layers and comprises a second doped epitaxial layer;
• and
• replacing the first dummy gate with a first gate structure, wherein the first gate structure extends continuously in the second direction to be wrapped around first portions of the first semiconductor layers between the first source/drain feature and the second source/drain feature, and wrapped around second portions of the second semiconductor layers between the third source/drain feature and the fourth source/drain feature.

A method of forming a semiconductor structure, comprising:

• forming a well region in a substrate;
• forming a first fin structure and a second fin structure over the well region, wherein each of the first fin structure and the second fin structure comprises first semiconductor layers and second semiconductor layers alternately stacked;
• forming a dummy gate over the first fin structure and the second fin structure;
• forming gate spacers on opposite sides of the dummy gate;
• etching the first fin structure to form a first source/drain trench and a second source/drain trench in the first fin structure and on the opposite sides of the dummy gate, and etching the second fin structure to form a third source/drain trench and a fourth source/drain trench in the second fin structure and on the opposite sides of the dummy gate;
• forming a first bottom dielectric layer in each of the first source/drain trench and the second source/drain trench;
• forming a first doped epitaxial layer over the first bottom dielectric layer in each of the first source/drain trench and the second source/drain trench, so as to form a first source/drain feature and a second source/drain feature in the first source/drain trench and the second source/drain trench, respectively;
• forming a second doped epitaxial layer in each of the third source/drain trench and the fourth source/drain trench, so as to form a third source/drain feature and a fourth source/drain feature in the third source/drain trench and the fourth source/drain trench, respectively;
• removing the dummy gate and the first semiconductor layers to form a gate trench;
• and
• forming a gate structure in the gate trench, wherein the gate structure comprises a gate dielectric layer wrapped around the second semiconductor layers and at least one metal layer over the gate dielectric layer.