Semiconductor device and method of fabricating the same

A semiconductor device comprising:

• a substrate comprising an active pattern;
• a device isolation layer defining the active pattern;
• a first channel structure and a second channel structure spaced apart from each other on the active pattern;
• a gate electrode on the first channel structure and the second channel structure;
• a gate insulating layer between the gate electrode and the first channel structure and between the gate electrode and the second channel structure;
• and
• a separation structure between the first channel structure and the second channel structure,
• wherein the first channel structure includes a first plurality of semiconductor patterns having four surfaces and the second channel structure includes a second plurality of semiconductor patterns having four surfaces,
• wherein an upper surface of the separation structure is higher than an upper surface of a n uppermost semiconductor pattern among the first plurality of semiconductor patterns and the second plurality of semiconductor patterns,
• wherein the gate insulating layer surrounds the four surfaces of each semiconductor pattern of the first plurality of semiconductor patterns and the second plurality of semiconductor patterns, and
• wherein a portion of side surface of the separation structure is exposed from the gate insulating layer.

A semiconductor device comprising:

• a substrate comprising a first active pattern and a second active pattern, the first active pattern and the second active pattern being defined by a device isolation layer;
• a first channel structure on the first active pattern and a second channel structure on the second active pattern;
• source/drain patterns connected to the first channel structure and the second channel structure;
• a first gate electrode on the first channel structure and a second gate electrode on the second channel structure;
• a gate insulating layer between the first gate electrode and the first channel structure and between the second gate electrode and the second channel structure;
• and
• a separation structure between the first channel structure and the second channel structure,
• wherein the first channel structure includes a first plurality of semiconductor patterns having four surfaces and the second channel structure includes a second plurality of semiconductor patterns having four surfaces,
• wherein the gate insulating layer surrounds the four surfaces of each semiconductor pattern of the first plurality of semiconductor patterns and the second plurality of semiconductor patterns,
• wherein an upper surface of the separation structure is higher than an upper surface of an uppermost semiconductor pattern among the first plurality of semiconductor patterns and the second plurality of semiconductor patterns, and
• wherein a portion of a side surface of the separation structure contacts the gate insulating layer, and the rest of the side surface of the separation structure contacts the first gate electrode and the second gate electrode in a horizontal point of view.