Integrated circuit device

An integrated circuit device comprising:

• a plurality of nanosheet stack structures disposed in rows in a first horizontal direction and in columns in a second horizontal direction that is different from the first horizontal direction, wherein each nanosheet stack structure of the plurality of nanosheet stack structures comprises a respective plurality of nanosheets;
• a plurality of source/drain regions connected to ends of the plurality of nanosheets included in each nanosheet stack structure of the plurality of nanosheet stack structures;
• a plurality of gate electrodes on the plurality of nanosheet stack structures, wherein the plurality of gate electrodes extend in the second horizontal direction and spaced apart from each other in the first horizontal direction;
• a plurality of upper sheet separation walls, each upper sheet separation wall of the plurality of upper sheet separations walls extending in the first horizontal direction and a vertical direction between adjacent nanosheet stack structures and between adjacent source/drain regions, wherein the plurality of upper sheet separation walls are spaced apart from each other in the second horizontal direction;
• a plurality of backside via contacts, each backside via contact of the plurality of backside via contacts being connected to two or more source/drain regions of the plurality of source/drain regions;
• a plurality of backside wiring lines, each backside wiring line of the plurality of backside wiring lines being connected to ends of respective backside via contacts of the plurality of backside via contacts;
• and
• a plurality of lower sheet separation walls, each lower sheet separation wall of the plurality of lower sheet separation walls extending in the first horizontal direction and the vertical direction between a pair of adjacent backside via contacts of the plurality of backside via contacts and between a pair of adjacent backside wiring lines of the plurality of backside wiring lines, wherein the plurality of lower sheet separation walls overlap the plurality of upper sheet separation walls in the vertical direction, and contact the plurality of upper sheet separation walls.

An integrated circuit device comprising:

• a plurality of nanosheet stack structures in rows and columns in a first horizontal direction and a second horizontal direction that is different from the first horizontal direction, the plurality of nanosheet stack structures comprising a plurality of nanosheets;
• a plurality of source/drain regions connected to ends of the plurality of nanosheets included in the plurality of nanosheet stack structures;
• a plurality of gate electrodes extending in the second horizontal direction and spaced apart from each other in the first horizontal direction on the plurality of nanosheet stack structures;
• an interlayer insulating layer surrounding the plurality of nanosheet stack structures, the plurality of source/drain regions, and the plurality of gate electrodes;
• a plurality of upper sheet separation walls, each upper sheet separation wall of the plurality of upper sheet separation walls extending in the first horizontal direction and a vertical direction between adjacent nanosheet stack structures of the plurality of nanosheet stack structures in the second horizontal direction, between adjacent source/drain regions of the plurality of source/drain regions in the second horizontal direction, and between adjacent gate electrodes of the plurality of gate electrodes in the second horizontal direction, and spaced apart from each other in the second horizontal direction;
• a plurality of backside via contacts connected to a group of source/drain regions of the plurality of source/drain regions;
• a plurality of backside wiring lines connected to ends of respective backside via contacts of the plurality of backside via contacts;
• a plurality of lower sheet separation walls, each lower sheet separation wall of the plurality of lower sheet separation walls extending in the first horizontal direction and the vertical direction between a pair of adjacent backside via contacts of the plurality of backside via contacts in the second horizontal direction and a pair of adjacent backside wiring lines of the plurality of backside wiring lines in the second horizontal direction, overlapping the plurality of upper sheet separation walls in the vertical direction, and contacting the plurality of upper sheet separation walls;
• a backside insulating layer surrounding the plurality of lower sheet separation walls;
• and
• a device separation layer surrounding the backside insulating layer,
• wherein the plurality of upper sheet separation walls have a tapered shape with a horizontal width that narrows in the second horizontal direction from first ends of the plurality of upper sheet separation walls to second ends of the plurality of upper sheet separation walls,
• wherein the plurality of lower sheet separation walls having a tapered shape with a horizontal width that increases in the second horizontal direction from first ends of the plurality of lower sheet separation walls to second ends of the plurality of lower sheet separation walls, and
• wherein the second ends of the plurality of upper sheet separation walls face the first ends of the plurality of lower sheet separation walls.