Semiconductor device

A semiconductor device, comprising:

• a semiconductor substrate including a first active region, a second active region, and a third active region sequentially disposed along a first direction;
• a first source/drain region provided in the first active region;
• a second source/drain region provided in the second active region;
• a third source/drain region provided in the third active region;
• a first gate structure disposed on the first active region;
• a second gate structure disposed on the second active region;
• a third gate structure disposed on the third active region;
• and
• a semiconductor layer disposed between the second active region and the second gate structure,
• wherein the first source/drain region comprises a first lower portion and a first upper portion disposed on the first lower portion,
• wherein the third source/drain region comprises a second lower portion and a second upper portion disposed on the second lower portion,
• wherein a sidewall of the first upper portion is inclined with a sidewall of the first lower portion,
• wherein a sidewall of the second upper portion is inclined with a sidewall of the second lower portion, and
• wherein the semiconductor layer includes silicon-germanium (SiGe).

A semiconductor device, comprising:

• a semiconductor substrate including a cell array region and a peripheral circuit region, the peripheral circuit region including a first active region and a second active region;
• a device isolation layer defining a cell active region disposed on the cell array region, the first active region, and the second active region;
• a bit line structure crossing the cell active region disposed on the cell array region;
• a first source/drain region provided in the first active region;
• a second source/drain region provided in the second active region;
• a first gate structure disposed on the first active region;
• a semiconductor layer having a lattice constant different from a lattice constant of the semiconductor substrate and disposed on the second active region;
• and
• a second gate structure disposed on the semiconductor layer,
• wherein the first source/drain region comprises a first lower portion and a first upper portion disposed on the first lower portion,
• wherein the first lower portion includes a first sidewall facing the second source/drain region, and
• wherein the first upper portion includes a second sidewall connected to the first sidewall of the first lower portion and inclined with the first sidewall.