Semiconductor device
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu Ying CHEN, Yuyuan HUANG
Life of this patent
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Abstract
A method of forming a semiconductor device comprises the following steps. A first active region and a second active region are formed over a substrate. An isolation feature is formed over the substrate and between the first active region and the second active region along a direction. A first gate structure is formed over the first active region and a second gate structure over the second active region. A gate isolation feature is formed disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion over the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a k value less than about 4.
Claims20
A method of forming a semiconductor device, comprising:
- forming a first active region and a second active region over a substrate;
- forming an isolation feature over the substrate and between the first active region and the second active region along a direction;
- forming a first gate structure over the first active region and a second gate structure over the second active region;
- and
- forming a gate isolation feature disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion over the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a k value less than about 4.
A method of forming a semiconductor device, comprising:
- forming a first active region and a second active region over a substrate;
- forming an isolation feature over the substrate and between the first active region and the second active region along a direction;
- forming a first gate structure over the first active region and a second gate structure over the second active region;
- forming a source/drain feature over the substrate;
- forming a contact etch stop layer (CESL) extending along a sidewall of the first gate structure and a sidewall of the second gate structure;
- forming an interlayer dielectric (ILD) layer over the CESL, wherein the CESL between the ILD layer and the source/drain feature comprises a non-linear profile;
- and
- forming a gate isolation feature disposed between the first gate structure and the second gate structure along the direction, wherein the gate isolation feature includes a first portion over the isolation feature and a second portion extending into the isolation feature, and the gate isolation feature includes SiOC with a k value less than about 4.
A semiconductor device, comprising:
- a first channel region and a second channel region extending over a substrate;
- an isolation feature disposed over the substrate and between the first channel region and the second channel region;
- a first gate stack disposed over the first channel region and the isolation feature;
- a second gate stack disposed over the second channel region and the isolation feature;
- a gate spacer disposed along a sidewall of the first gate stack, wherein the first gate stack comprises a gate dielectric layer and a gate electrode over the gate dielectric layer, wherein a bottom surface of the gate spacer is lower than a top surface of the first channel region, wherein a dielectric constant of the gate spacer is less than a dielectric constant of the gate dielectric layer;
- and
- a gate isolation feature disposed between the first gate stack and the second gate stack, wherein the gate isolation feature has a first curved sidewall.
Dependencies are inferred from the claim text.