Integrated circuit device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorJhon-Jhy LIAW
Life of this patent
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Abstract
A method of manufacturing an integrated circuit device includes: forming a first semiconductor fin over a first conductivity type well region on a substrate; forming a first gate structure extending across the first semiconductor fin; forming a plurality of first epitaxial structures of the first conductivity type on the first semiconductor fin and at opposite sides of the first gate structure; forming a first conductive line extending across the first gate structure, wherein the first semiconductor fin has a wider width than the first conductive line.
Claims20
A device, comprising:
- a substrate;
- a first conductivity type well region on the substrate;
- a first semiconductor fin over the first conductivity type well region;
- a first gate structure overlying the first semiconductor fin, a first interface being present between a bottom surface of the first gate structure and an upper surface of the first semiconductor fin;
- a plurality of first epitaxial structures of a first conductivity type on the first semiconductor fin and at opposite sides of the first gate structure;
- and
- a first conductive line overlying the first gate structure, wherein the first semiconductor fin has a wider width than the first conductive line, and a second interface is present between a bottom surface of the first conductive line and an upper surface of the first gate structure.
A device, comprising:
- a semiconductor substrate;
- a first well on the semiconductor substrate;
- a first channel pattern over the first well;
- a first gate structure wrapping around the first channel pattern;
- a plurality of first epitaxial features at opposite sides of the first gate structure having an opposite conductivity type than a conductivity type of the first channel pattern;
- a second well on the semiconductor substrate;
- a second channel pattern over the second well, wherein the second channel pattern is offset from the first channel pattern in a first direction and in a second direction different than the first direction, such that a line extending in the first direction and passing through the first channel pattern would not pass through the second channel pattern and a line extending in the second direction and passing through the first channel pattern would not pass through the second channel pattern;
- a second gate structure wrapping around the second channel pattern;
- and
- a plurality of second epitaxial features at opposite sides of the second gate structure and having a same conductivity type as the second channel pattern, wherein, from a top view, the second channel pattern has a wider width than the first channel pattern along a lengthwise direction of the first gate structure.
An integrated circuit device, comprising:
- a semiconductor substrate;
- a first fin upwardly extending from a first well on the semiconductor substrate;
- a first gate structure extending across the first fin;
- a plurality of first epitaxial features at opposite sides of the first gate structure and having an opposite conductivity type than the first fin;
- a second fin upwardly extending from a second well on the semiconductor substrate;
- a second gate structure extending across the second fin;
- and
- a plurality of second epitaxial features at opposite sides of the second gate structure and having a same conductivity type as the second fin, wherein the second fin has a wider width than the first fin.
Dependencies are inferred from the claim text.