Integrated circuit structure with decoupling capacitor cell for power delivery network

An integrated circuit structure, comprising:

• a gate line extending over a semiconductor nanowire stack channel structure;
• a first trench contact laterally spaced apart from a first side of the gate line;
• a second trench contact laterally spaced apart from a second side of the gate line, the second side opposite the first side;
• a first conductive line over the first trench contact, over the gate line, and over the second trench contact, the first conductive line coupled to the first trench contact and to the second trench contact;
• and
• a second conductive line over the first trench contact, over the gate line, and over the second trench contact, the second conductive line coupled to the first trench contact and to the second trench contact, and the second conductive line parallel with and in a same metallization layer as the first conductive line.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a gate line extending over a semiconductor fin structure or a semiconductor nanowire stack channel structure;
• a first trench contact laterally spaced apart from a first side of the gate line;
• a second trench contact laterally spaced apart from a second side of the gate line, the second side opposite the first side;
• a first conductive line over the first trench contact, over the gate line, and over the second trench contact, the first conductive line coupled to the first trench contact and to the second trench contact;
• and
• a second conductive line over the first trench contact, over the gate line, and over the second trench contact, the second conductive line coupled to the first trench contact and to the second trench contact, and the second conductive line parallel with and in a same metallization layer as the first conductive line.