Method of manufacturing power semiconductor device including shielding region

A method of manufacturing a power semiconductor device, the method comprising:

• forming a lower drift layer of a first conductivity type on a base semiconductor layer;
• forming at least one shielding region in upper portions of the lower drift layer by doping with impurities of a second conductivity type different from the first conductivity type;
• forming an upper drift layer of the first conductivity type on the lower drift layer and the at least one shielding region;
• forming a source trench extending from an upper surface of the upper drift layer to a lower vertical level than a lower surface of the at least one shielding region;
• forming a pillar region of the second conductivity type along a bottom surface and an inner side surface of the source trench;
• forming a gate trench through the upper drift layer;
• and
• forming a gate electrode in the gate trench,
• wherein the gate trench is formed so as not to overlap the at least one shielding region in a vertical direction and extends into the upper drift layer.

A method of manufacturing a power semiconductor device, the method comprising:

• forming a lower drift layer of a first conductivity type on a base semiconductor layer of the first conductivity type, the lower drift layer comprising 4H—SiC;
• forming a pair of shielding regions of a second conductivity type different from the first conductivity type in upper portions of the lower drift layer, wherein an upper surface of each of the pair of shielding regions is coplanar with an uppermost surface of the lower drift layer;
• forming an upper drift layer of the first conductivity type on the lower drift layer and the pair of shielding regions, the upper drift layer comprising 4H—SiC;
• forming a base region of the second conductivity type on the upper drift layer;
• forming a source region of the first conductivity type on the base region;
• forming a pair of ohmic regions in portions of the source region and portions of the base region;
• forming a pair of source trenches by removing portions of the pair of ohmic regions, the upper drift layer, the lower drift layer, and the pair of shielding regions;
• forming a pillar region at a bottom surface of each of the pair of source trenches and a side pillar region at an inner side surface of each of the pair of source trenches, the pillar region comprising a bottom pillar region;
• forming a gate trench through the source region and the base region into the upper drift layer;
• forming a gate electrode in the gate trench;
• and
• forming a source electrode covering the source region and the pair of ohmic regions,
• wherein the gate trench and the pair of source trenches are formed to be non-overlapping in a vertical direction with respect to the pair of shielding regions.