P-type region integration for enhanced square-cell sic mosfet

A semiconductor structure comprising:

• a semiconductor substrate of a first conductivity type having an upper surface and a bottom surface, the semiconductor substrate including a silicon carbide substrate;
• a plurality of unit cells disposed on the upper surface of the semiconductor substrate, each unit cell including:
• a base region of a second conductivity type, and
• a source region of the first conductivity type disposed above the base region;
• and
• a plurality of protective doped regions of the second conductivity type, wherein each protective doped region is positioned between at least two neighboring unit cells electrically connecting the base region of each of the at least two neighboring unit cells.

A semiconductor structure comprising:

• a semiconductor substrate of a first conductivity type having an upper surface and a bottom surface, the semiconductor substrate including a silicon carbide substrate;
• a plurality of unit cells disposed on the upper surface of the semiconductor substrate, each unit cell including:
• a base region of a second conductivity type, and
• a source region of the first conductivity type disposed above the base region;
• and
• a plurality of protective doped regions of the second conductivity type, wherein the protective doped regions extend laterally between adjacent base regions of neighboring unit cells to form a continuous protective network arranged in a geometric pattern.