Integrated circuit and method for manufacturing same

An integrated circuit comprising:

• a substrate at least whose uppermost plane is a single crystal of silicon carbide with a vertical plane intersecting the uppermost plane and extending downwardly therefrom, and a lower plane substantially parallel to the uppermost plane and intersecting the vertical plane;
• a single-crystal graphene layer provided in contact with the uppermost plane of the substrate;
• and
• a gallium nitride layer provided on the substrate,
• wherein an active element portion formed on the gallium nitride layer and a short-gate-length transistor using the graphene layer as a gate are integrally formed, and
• wherein the short-gate-length transistor comprises:
• a gate electrode at the edge where the graphene layer intersects the vertical plane;
• an insulating film formed to cover at least the vertical plane and edges of the graphene layer;
• a two-dimensional semiconductor layer formed to cover the uppermost plane, the vertical plane, and the lower plane, the two-dimensional semiconductor layer being also formed to cover the graphene layer and/or insulating film at a portion where the graphene layer and/or insulating film exists;
• a source electrode provided at a portion where the uppermost plane is covered by the two-dimensional semiconductor layer;
• and
• a drain electrode provided at a portion where the lower plane is covered by the two-dimensional semiconductor layer.

A method for manufacturing an integrated circuit in which a short-gate-length transistor and an antenna element are integrally formed, comprising:

• a step of preparing a substrate at least whose uppermost plane is a single crystal of silicon carbide;
• a step of forming a graphene layer on the uppermost plane of the substrate;
• in the area of the first region of the substrate where the short-gate-length transistor is formed:
• a step of forming, by microfabrication, on the substrate, a vertical plane intersecting the uppermost plane and extending downward therefrom, and a lower plane substantially parallel to the uppermost plane and intersecting the vertical plane, while leaving a portion of the graphene layer intact, by removing the graphene layer and the upper portion of the substrate from the other portion;
• a step of depositing an insulating film to cover at least the vertical plane and edges of the graphene layer;
• a step of depositing a two-dimensional semiconductor layer to cover the uppermost plane, the vertical plane, and the lower plane, and to also cover the graphene layer and/or insulating film where the graphene layer and/or insulating film exists;
• a step of forming an electrode overlaid on a portion where the graphene layer is covered by the two-dimensional semiconductor layer, and forming an electrode overlaid on a portion where the lower plane is covered by the two-dimensional semiconductor layer;
• and
• a step of forming an antenna element by patterning the graphene layer, in the second region, where the antenna element is formed, of the substrate.

A method for manufacturing an integrated circuit in which a short-gate-length transistor and an active element formed in a gallium nitride layer are integrally formed, comprising:

• a step of preparing a substrate at least whose uppermost plane is a single crystal of silicon carbide;
• a step of forming a graphene layer on the uppermost plane of the substrate;
• a step of epitaxially growing a gallium nitride layer using the graphene layer as a buffer layer;
• in the area of the first region of the substrate where the short-gate-length transistor is formed:
• a step of removing the gallium nitride layer to expose the graphene layer;
• a step of forming, by microfabrication, on the substrate, a vertical plane intersecting the uppermost plane and extending downward therefrom, and a lower plane substantially parallel to the uppermost plane and intersecting the vertical plane, while leaving a portion of the graphene layer intact, by removing the graphene layer and the upper portion of the substrate from the other portion;
• a step of depositing an insulating film to cover at least the vertical plane and edges of the graphene layer;
• a step of depositing a two-dimensional semiconductor layer to cover the uppermost plane, the vertical plane, and the lower plane, and to also cover the graphene layer and/or insulating film at a portion where the graphene layer and/or insulating film exists;
• a step of forming an electrode overlaid on a portion where the graphene layer is covered by the two-dimensional semiconductor layer, and forming an electrode overlaid on a portion where the lower plane is covered by the two-dimensional semiconductor layer;
• and
• a step of forming an active element portion including an amplifier on the remaining gallium nitride layer.

A method for manufacturing an integrated circuit in which a short-gate-length transistor and an active element formed in a gallium nitride layer are integrally formed, comprising:

• a step of preparing a substrate at least whose uppermost plane is a single crystal of silicon carbide;
• a step of forming a graphene layer on the uppermost plane of the substrate;
• a step of removing a portion of the graphene layer;
• a step of epitaxially growing a gallium nitride layer in the area where the graphene layer has been removed;
• and
• a step of forming an active element portion including an amplifier in the gallium nitride layer,
• in a region where the graphene layer remains:
• a step of forming, by microfabrication, on the substrate, a vertical plane intersecting the uppermost plane and extending downward therefrom, and a lower plane substantially parallel to the uppermost plane and intersecting the vertical plane, while leaving a portion of the graphene layer intact, by removing the graphene layer and the upper portion of the substrate from the other portion;
• a step of depositing an insulating film to cover at least the vertical plane and edges of the graphene layer;
• a step of depositing a two-dimensional semiconductor layer to cover the uppermost plane, the vertical plane, and the lower plane, and to also cover the graphene layer and/or insulating film at a portion where the graphene layer and/or insulating film exists;
• and
• a step of forming an electrode overlaid on a portion where the graphene layer is covered by the two-dimensional semiconductor layer, and forming an electrode overlaid on a portion where the lower plane is covered by the two-dimensional semiconductor layer.