Memory cell with offset interconnect via

An integrated chip, comprising:

• a first electrode disposed over a substrate and having a bottom surface in contact with a lower interconnect;
• a second electrode;
• a data storage structure located between the first electrode and the second electrode;
• and
• an interconnect via disposed on the second electrode, wherein a projection of a bottom surface of the interconnect via has a first center that is offset from a second center of a projection of the bottom surface of the first electrode.

An integrated chip, comprising:

• a lower electrode disposed over a substrate and having a bottom surface in contact with a lower interconnect;
• an upper electrode over the lower electrode, wherein the upper electrode comprises an outer region and an inner region that is recessed below the outer region, the outer region wrapping around the inner region along a closed loop in a plan view;
• a metal oxide material located between the lower electrode and the upper electrode;
• and
• an interconnect having a bottom surface contacting the upper electrode within the outer region and laterally outside of the inner region.