Stacked three-transistors memory cells, compute-in-memory integrated circuits, and computing devices

Abstract

Three-dimensional three-transistors (3T) memory cells having three thin film transistors and a capacitor that are stacked on top of each other in a three-dimensional configuration. An array of a plurality of the three-transistors memory cell can be used to form a memory array. The three-transistors memory cell can be implemented in an integrated circuit as a top-end-of-line layer disposed on top of the back-end-of-line layer of the integrated circuit. Such an integrated circuit may be configured to form an embedded dynamic random-access memory (eDRAM) compute-in-memory integrated circuit. The eDRAM compute-in-memory may be used in a computing device. The computing device may be configured for executing an artificial intelligence neural network where the nodes of the neural network map directly to the array of stacked 3T memory cells in the (eDRAM) compute-in-memory.

Dependencies are inferred from the claim text.