Device, system and methods for pll control

A device comprising:

• a phase acquisition circuit to receive a reference clock, a low-noise oscillator signal and a local oscillator signal, the phase acquisition circuit to generate a delayed version of the local oscillator signal, and the phase acquisition circuit to sample the reference clock with the delayed local oscillator signal to generate an internal reference signal and the phase acquisition circuit to sample the low-noise oscillator signal with the delayed local oscillator signal to generate an internal low-noise oscillator signal, and the phase acquisition circuit to sample the local oscillator signal with a delayed version of the local oscillator signal to generate an internal local oscillator signal;
• a first feedback circuit;
• a second feedback circuit;
• and
• a divider circuit,
• wherein the first feedback circuit to receive the internal reference signal and the first feedback circuit comprising:
• a first digital phase-locked loop (DPLL) circuit, the first DPLL circuit to receive the internal reference signal and to generate a first DPLL output signal,
• wherein the second feedback circuit to receive the internal low-noise oscillator signal and a sampled version of the internal local oscillator signal, the second feedback circuit comprising:
• a second DPLL circuit, the second DPLL circuit to receive the internal low-noise oscillator signal and to generate a second DPLL output signal, and
• wherein the divider circuit to receive the first DPLL output signal and the local oscillator signal and to generate a divided output clock signal.

A method comprising:

• detecting a first phase relationship between an input reference and a local oscillator signal to generate an internal reference signal;
• detecting a second phase relationship between a low-noise oscillator signal and the local oscillator signal to generate an internal low-noise oscillator signal;
• detecting a third phase relationship between a delayed version of a local oscillator signal and the local oscillator signal;
• generating a first digital phase-locked-loop (DPLL) output based on the first phase relationship;
• generating a second DPLL output based on the second phase relationship and based on the third phase relationship;
• and
• generating a divided output clock based on the first DPLL output.