A wide-band, multi-phase phase-locked loop circuit

A method of operating a wide-band, multi-phase phase-locked loop (PLL) circuit, comprising:

• selecting an operating mode for a reconfigurable and programmable multi-phase phase frequency detector (PFD) and reconfigurable charge pump controller (CPC) circuit (PFD-CPC circuit) based on one or more defined parameters;
• wherein the operating mode is a single-phase mode or multi-phase mode, and the PFD-CPC circuit includes a multi-phase PFD and a plurality of identical slices of the reconfigurable CPC and configured to operate in either the single-phase or the multi-phase mode to reduce phase noise and jitter contribution of one or more forward path loop components within a targeted frequency band;
• providing a high-frequency reference signal to the PFD-CPC circuit coupled to an output of a divider circuit and a voltage-controlled oscillator (VCO);
• and
• maximizing bandwidth and suppressing phase noise and jitter contribution from one or more forward path loop components within a targeted frequency band based on the operating mode.