Apparatus and techniques for clock signal generation

A method for clock generation, comprising:

• providing, via an input transistor, an input voltage to a charge pump;
• generating a boosted voltage via the charge pump based on the input voltage;
• driving, via a first gate drive circuit, a gate of a first transistor to provide the boosted voltage to an auxiliary clock (CKaux) node and generate a CKaux signal, the CKaux signal being provided to a gate of the input transistor;
• and
• driving, via a second gate drive circuit, a gate of a second transistor to provide the boosted voltage to a boosted clock (CKbst) node and generate a CKbst signal, the second gate drive circuit being separate from the first gate drive circuit.

A sample-and-hold circuit, comprising:

• a sampling transistor coupled to an input voltage node;
• and
• a clock generation circuit comprising:
• a charge pump including a capacitive element;
• a first transistor coupled between a first terminal of the capacitive element and an auxiliary clock (CKaux) node;
• a second transistor coupled between the first terminal of the capacitive element and a boosted clock (CKbst) node, CKbst node being coupled to a gate of the sampling transistor;
• an input transistor with a gate coupled to the CKaux node, a drain coupled to the input voltage node, and a source coupled to a second terminal of the capacitive element;
• a first gate drive circuit coupled to a gate of the first transistor;
• and
• a second gate drive circuit coupled to a gate of the second transistor, the second gate drive circuit being separate from the first gate drive circuit.