Chip data transfer interface and semiconductor device

A semiconductor device, comprising:

• a first chip, having a chip data transfer interface;
• and
• a second chip, coupled to the chip data transfer interface;
• wherein the chip data transfer interface comprises:
• a data receiving circuit, configured to receive a parallel input data according to a first operation clock, and send a parallel output data;
• a data transfer circuit, coupled to the data receiving circuit, configured to receive the parallel output data based on a second operation clock, and send a serial data;
• a clock supply circuit, coupled to the data receiving circuit and the data transfer circuit, the clock supply circuit configured to generate a system clock and the second operation clock based on a source clock;
• and
• a phase modulation circuit, coupled to the data receiving circuit and the clock supply circuit, the phase modulation circuit configured to receive the system clock and the first operation clock, and allowing the system clock to be in phase with the first operation clock;
• wherein when the system clock is in phase with the first operation clock, the clock supply circuit is configured to output the second operation clock, and the second operation clock is synchronized with the first operation clock.