Frequency doubler circuit

A frequency doubler circuit comprising:

• first and second input terminals for receiving an input voltage signal at a first frequency;
• a first pair of transistors connected between a supply line and a first node, the first pair of transistors having gates AC coupled to the respective first and second input terminals;
• a second pair of transistors connected between a common line and a second node, the second pair of transistors having gates AC coupled to the respective first and second input terminals;
• an output matching circuit having first and second output terminals for providing an output voltage signal at a second frequency;
• an amplifier having a first input connected to the output matching circuit, a second input connected to a target voltage input, and an output connected to provide a bias voltage to the gates of one of the first and second pairs of transistors;
• a first common gate transistor connected between the first node and a first input of the output matching circuit;
• and
• a second common gate transistor connected between the second node and a second input of the output matching circuit.

A method of operating a frequency doubler circuit, the method comprising:

• providing an input voltage signal at a first frequency at first and second input terminals;
• providing bias voltage signals to gates of first and second pairs of transistors and gates of first and second common gate transistors;
• and
• providing an output voltage signal at first and second output terminals at a second frequency that is double the first frequency,
• wherein the frequency doubler circuit includes:
• the first and second input terminals for receiving an input voltage signal,
• the first pair of transistors connected between a supply line and a first node, the gates of the first pair of transistors being AC coupled to the first and second input terminals, respectively,
• the second pair of transistors connected between a common line and a second node, the second pair of transistors having gates that are AC coupled to the respective first and second input terminals,
• an output matching circuit that includes the first and second output terminals,
• an amplifier having a first input connected to the output matching circuit, a second input connected to a target voltage input, and an output connected to provide a bias voltage to the gates of one of the first and second pairs of transistors,
• the first common gate transistor, wherein the first common gate transistor is connected between the first node and a first input of the output matching circuit, and
• the second common gate transistor, wherein the second common gate transistor is connected between the second node and a second input of the output matching circuit.