Multi-output voltage converter

A multi-output voltage converter comprising:

• a plurality of converting circuits, each of the plurality of converting circuits including a inductor and a power transistor and configured to generate a output voltage at a respective output node by converting an input voltage based on a respective driving signal, each power transistor of the plurality of converting circuits configured to pull-up a respective switching node based on the respective driving signal, each switching node of the plurality of converting circuits being coupled to a first end of the respective inductor;
• a strength adjusting signal generator configured to generate a plurality of strength adjusting signals based on transition timings of a plurality of internal driving signals including a first internal driving signal and a second internal driving signal;
• and
• a plurality of driving circuits including a first driving circuit and a second driving circuit, the first and second driving circuits configured to generate a first driving signal and a second driving signal based on a first internal driving signal and a second internal driving signal, wherein the first driving signal drives a first power transistor and the second driving signal drives a second power transistor,
• wherein, upon detecting that a first transition timing of the first internal driving signal is simultaneous with a second transition timing of the second internal driving signal, each of the first driving circuit associated with a first driving signal and the second driving circuit associated with a second driving signal is configured to reduce a driving strength of a respective one of the first power transistor and the second power transistor, based on the first internal driving signal, the second internal driving signal and a first strength adjusting signal indicating that the first transition timing is simultaneous with the second transition timing.

A multi-output voltage converter comprising:

• a first converting circuit including a first inductor and a first power transistor, the first converting circuit configured to generate a first output voltage at a first output node by converting an input voltage based on a first driving signal, the first power transistor configured to pull-up a first switching node coupled to a first end of the first inductor based on the first driving signal;
• a second converting circuit including a second inductor and a second power transistor, the second converting circuit configured to generate a second output voltage at a second output node by converting the input voltage based on a second driving signal, the second power transistor configured to pull-up a second switching node coupled to a first end of the second inductor based on the second driving signal;
• a shifting signal generator configured to generate a shifting signal based on a first transition timing of a first internal driving signal and a second transition timing of a second internal driving signal;
• a first driving circuit configured to generate the first driving signal based on the first internal driving signal;
• and
• a second driving circuit configured to generate the second driving signal by shifting the second transition timing of the second internal driving signal based on the shifting signal indicating that the first transition timing is simultaneous with the second transition timing.